A modern IC design, an IP (intellectual property) cell in the IC (integrated circuit) core area may communicate and exchange data with certain IP cells in the IC core area and certain part(s) in the outer I/O (input/output) ring and thus need to stay within some close proximity of the corresponding portion in the I/O ring. During the early design planning stages where design data are scarce and incomplete at best, an architect may have to determine what the fabric need to look like in order to meet various criteria, such as functional requirements, I/O conductivity or connectivity, fabric configuration, etc. Modern electronic designs (e.g., SOCs (system on chip)) or include functional IPs (intellectual property) such as interface cores, CPUs (central processing units), encorder, decoder, memory interfaces, etc. that may need to interconnected in some fashion so as to move data among these functional IPs. A fabric includes such interconnections of such electronic design together with other components such as arbiters to resolve contention for a resource, queues, etc.
Moreover, some of the design criteria may compete with some other design criteria, and the conflicting criteria may further exacerbate the challenges. Traditional approaches typically receive, for example, the functional requirements for a design, model the design in terms of the flow of the signals and the logic operations on these signals in RTL (register transfer level), synthesize the RTL, and perform prototyping using the netlist from the synthesis. Nonetheless, such conventional approaches may not properly serve prototyping, IO planning, feasibility analysis, or floorplanning in early design stages where the details of the design are lacking or to be determined. Therefore, what is needed is a method, system, and computer program product for implementing physical design decomposition with custom connectivity.